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We are seeking a Senior Electrical Engineer who will support various ongoing programs within the Software, Cyber, and Intelligence Division. You will support the FPGA/ASIC Firmware Verification efforts to review designs, documents, implement and test software/firmware for commercial-off-the-shelf (COTS) and custom electronic hardware for laboratory and/or military applications. You must be self-motivated, team-orientated, and possess flexibility given our dynamic verification and validation environment. The duties will include, but not be limited to, verifying and testing FPGA/ASIC design, assembly, integration, and embedded firmware, electronic assemblies, and systems.
You will perform dynamic constrained-random verification of FPGA devices with predictive modeling and scoring of device behavior. Great communication skills are required as you will deliver code/functional coverage metrics including defect counts to customer(s). Identification of risks and the ability to formulate mitigation strategies and plans is required.
Required
- BS degree in Electrical Engineering or related technical degree
- 8 years of related technical experience
- VHDL and/or Verilog Experience
- Knowledge of UVM (IEEE 1800.2 ‐2017) standard/methodology
- Questa ModelSim/QuestaSim experience or possibly Synopsis Synplify expertise
- Must have the ability to obtain and maintain a security clearance
Disability Accommodation for Applicants
- Intuitive Research and Technology Corporation is an Equal Employment Opportunity employer and provides reasonable accommodation for qualified individuals with disabilities and disabled veterans in its job application procedures. If you have any difficulty using our online system and you need an accommodation due to a disability, you may use the following alternative email address or phone number to contact us about your interest in employment at INTUITIVEhr@irtc-hq.com or 256-922-9300. Our process is to respond and to work with the requestor to identify a workable accommodation to the application process.