Are you an experienced Architect for IP/IC development with Strong Front-end domain knowledge and would you like to make the next step in your career?Are you able to drive and lead our high-performance team working on next generation of Radar Chips with exacting requirements of reliability for automotive domain?Then, I would suggest that you keep on reading further!
- KEY RESPONSIBILITIES
- To drive technically FE integration of SoC from microarchitecture upto the TO working closely with IC and System architects
- To work closely with Subsystem lead for the input of soft IP deliveries as per the architecture requirements
- To lead the FE integration using Industry standard tools such as Magillem
- To ensure design is clean with respect to all static quality checks e.g. Lint, CDC, RDC
- To work closely with DFT teams and define IC top RTL including IO muxing, DFT RTL blocks and other necessary glue logic for SoC Top Front-end
- To technically drive Change Management process for RTL changes anticipated as an outcome of requirement changes as well as feedback from Verification.
- To drive power numbers and analyse the same from architecture, to RTL and through out implementation flow and define means to optimize with the help of various domain leads.
- To assist and review functional, DFT constraints for the Physical design timing closure
- PROFILE
- Candidate with 15+yrs of experience in FE Designs with hands on integration experience on SoCs containing multiple ARMs, FlexNoc, and interfaces such as MIPI/Ethernet/SPI.
- Hand-on experience in using industry standard tools for checking LINT and Clock Domain Crossing for digital IPs/subsystems or SoC
- Candidate with proven ability to automate and improve the methodology
- Candidate with strong collaboration skill being a cross functional horizonal role
- BE/ME/B.Tech/M.Tech from Reputed institution
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