About Rain:
At Rain AI, we’re creating a future with abundant and scalable artificial intelligence. We're building the world’s most cost and energy efficient hardware for AI. Our products achieve an order of magnitude improvement over the status quo by co-designing every layer of the AI stack, from circuits to algorithms. Our ultimate goal is to become the dominant hardware company of the AI era. Rain AI is currently a Series A stage startup and backed by world leaders in AI. Our seed round was led by Sam Altman (OpenAI).
In addition, our current VC partners include Y Combinator, Daniel Gross, Jaan Tallinn, Founders X Fund, Airbus Ventures, Liquid 2 Ventures and Deepwater.
About the role:
We are looking for a Principal Circuit Design Engineer to join our custom team. You will be designing and implementing low-power, high performance, area-efficient compute-in memory circuits and architectures. This is a highly visible role where you will closely collaborate with layout, CAD, physical design teams.
Responsibilities:
Develop custom digital circuits for novel high-speed and low-power compute-in memory designs
Collaborate with an exceptional logic/architecture team to formulate design specifications
Innovate and incorporate special circuits and features to achieve better PPA
Own validation, margin simulation, and characterization flows for block development and sign-off
Work closely with layout team for planning and support and review layout for optimality
Participate in test chip design efforts to explore and validate new ideas and approaches
Work closely with the architecture and IC design teams to integrate SRAM macros into an in-memory computing accelerator
Mentor, guide, and direct other designers, while being hands-on in digital circuit design
Qualifications:
10+ years of hands-on experience in design of memories in advanced nodes (3nm/5nm) with a focus on in-memory computing with SRAM
Strong track record of offering innovative solutions (papers, patents), good understanding of technology roadmap
Deep understanding of digital and SRAM circuit and layout design concepts in finFET-based CMOS technologies
Exposure to complete design cycle of SRAM memory and compiler development
Solid hands-on experience in SRAM design involving SPICE simulations, variation/selftime/bitcell/SA analysis
Ability to close design to the specs by running and developing various flows like ESPCV, EM, IR, Noise, and static timing analysis (STA)
Project and people management skills; experience organizing team goals, building efficient processes and resolving conflict in technical work
Exhibit a high degree of motivation and independence
Strong communication skills, both written and verbal
Preferred Qualifications:
Experience in AI accelerators and data-flow architectures and understanding of state of the art near- and in-memory computing fabrics
Familiarity with state of the art deep learning models and their hardware implementations
Set up and maintained EDA tool flows
Familiarity with physical design for custom circuits
Our Benefits:
Medical Insurance with 100% coverage of employee premiums
Dental and Vision Insurance
401k match
Unlimited PTO + all federal holidays
Two weeks off around Christmas and New Years
Summer “shutdown”: one week-off for all employees
Work from anywhere in the United States
$500 of office equipment per year
And more!
Compensation Range: $220K - $260K
