Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We are seeking a highly experienced Staff Testbench Methodology Engineer with deep expertise in UVM (Universal Verification Methodology) and CPU design/verification. In this senior role, you will lead the development, optimization, and implementation of advanced UVM-based testbench methodologies for CPU architectures and other complex hardware systems. You will mentor junior engineers, define best practices, and drive innovation in our verification processes, ensuring that our products meet the highest standards of quality and reliability.This role ishybrid, based out of Austin, TX or Santa Clara, CA.We welcome candidates at various experience levels for this role.
During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Responsibilities:
- Leadership and Strategy:
- Lead the design and implementation of UVM-based test bench methodologies, with a focus on CPU verification.
- Define and drive the verification strategy for CPU designs, ensuring alignment with overall product development goals.
- Mentor and guide junior engineers in best practices and advanced verification techniques.
- Design and Development:
- Architect and develop complex, scalable UVM test benches for CPU and other hardware systems.
- Develop C++ checker methodology that can be developed at UVM unit TBs and exported to Core TBs.
- Develop/maintain Register verification methodologies using UVM RAL and/or C++ models.
- Collaborate closely with CPU design and architecture teams to understand intricate verification requirements and ensure comprehensive test coverage.
- Directly assist in verification execution as needed.
- Methodology Optimization:
- Continuously refine and optimize UVM methodologies to enhance efficiency, coverage, and scalability for CPU verification.
- Identify and solve critical bottlenecks in the verification process, leading efforts to implement innovative solutions.
- CPU-Specific Testing:
- Lead the development of test strategies specifically for verifying CPU functionalities, including instruction set verification, microarchitecture features, and performance validation.
- Ensure that all UVM test benches are rigorously validated and capable of accurately testing and verifying complex CPU designs under diverse conditions.
- Automation and Tooling:
- Spearhead the development and integration of advanced automation tools to streamline UVM test bench setup, configuration, and execution and debug for CPU testing.
- Collaborate with cross-functional teams to ensure that UVM test benches are compatible with and leverage existing verification frameworks and tools.
- Documentation and Training:
- Author and maintain comprehensive, advanced-level documentation on UVM methodologies specific to CPU verification, including best practices and procedural guidelines.
- Lead training sessions and workshops to disseminate up to date knowledge and expertise on UVM and CPU verification to engineering teams.
- Collaboration and Communication:
- Act as a primary point of contact for UVM and CPU verification within the company, working closely with design, software, and QA teams to align verification strategies with broader company objectives.
- Present findings, performance metrics, and improvement plans related to UVM test benches and CPU verification to senior management and other stakeholders.
Experience & Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field
- 8-12 years of experience in testbench design and methodology engineering, with a significant focus on UVM and CPU verification
- Proven track record in leading the development and optimization of UVM test benches for CPU and other complex hardware systems
- Deep expertise in UVM, CPU architectures, test methodologies, tools, and best practices
- Proficiency in programming languages commonly used in hardware verification (e.g., SystemVerilog, Python)
- Strong leadership and mentorship skills, with experience guiding teams and influencing strategy
- Excellent problem-solving abilities, with a focus on innovative solutions to complex challenges
- Exceptional communication skills, both written and verbal, with the ability to convey complex technical concepts to diverse audiences.
- Experience with ISO-26262 or DO-254 is preferred
- Knowledge of hardware-in-the-loop (HIL) and software-in-the-loop (SIL) testing methodologies is preferred
- Experience with C/C++ is preferred
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S.
government.Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S.
government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.
